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C HAPTER 5: T IMING A NALYSIS AND D ESIGN O PTIMIZATION
R UNNING THE T IME Q UEST T IMING A NALYZER
The TimeQuest analyzer reports results only when requested. You can
customize each report on demand to display specific timing information.
Specifying Timing Constraints
You can make individual timing constraints for individual entities, nodes,
and pins with the Constraints menu of the TimeQuest analyzer. Individual
timing assignments override project-wide requirements. You can also
asssign timing exceptions to nodes and paths to avoid reporting of incorrect
or irrelevant timing violations. The TimeQuest analyzer supports
point-to-point timing constraints, wildcards to identify specific nodes when
making constraints, and assignment groups to make individual constraints
to groups of nodes.
You can make the following types of individual timing assignments in the
TimeQuest analyzer:
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Clock settings —Allow you to perform an accurate multiclock timing
analysis by defining the timing requirements and relationship of all
clock signals in the design. The TimeQuest analyzer supports both
single-clock and multiclock frequency analysis.
Clock uncertainty assignments— Allow you to specify the expected
clock setup or hold uncertainty (jitter) that should be used when
performing setup and hold checks. The TimeQuest analyzer subtracts
the specified setup uncertainty from the data required time when
calculating setup checks and adds the specified hold uncertainty to the
data required time when calculating hold checks.
Input and Output Delays— Allow you to specify external device or
board timing parameters by specifying the required data arrival times
at specified input and output ports relative to the clock.
You can make the following types of individual timing exceptions as
assignments in the TimeQuest analyzer:
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Multicycle paths —Paths between registers that require more than one
clock cycle to become stable. You can set multicycle paths to instruct the
analyzer to relax its measurements and avoid incorrect setup or hold
time violations.
False paths —You can designate as false paths any paths in the design
which the timing analyzer disregards during analysis and reporting. By
default, the Quartus II software cuts (directs the timing analyzer to
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I NTRODUCTION TO THE Q UARTUS II S OFTWARE
A LTERA C ORPORATION
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相关PDF资料
SW-QUARTUS-SE-FLT SUBSCRIPTION FLOATALL REPL
SW006012 C COMPILER FOR DSPIC30F FAMILY
SW006013 C COMPILER MPLAB FOR DSPIC DSC
SW006015 C COMPILER MPLAB C32
SW300003-EVAL LIBRARY SOFT MODEM-EVAL ONLY
SW300010-EVAL SPEECH RECOG LIBRARY-EVAL ONLY
SW300040-EVAL LIBRARY NOISE SUPPR-EVAL ONLY
SW300060-EVAL LIBRARY ACOUSTIC ECHO-EVAL ONLY
相关代理商/技术参数
SW-QUARTUS-SE-FLT 功能描述:开发软件 FLOATING LICENSE FOR QUARTUS II RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
SWR 制造商:RUBYCON 制造商全称:RUBYCON CORPORATION 功能描述:METALLIZED POLYESTER FILM CAPACITORS
SWR-1 制造商:Sunhayato 功能描述:
SWR100MD 功能描述:基准电压& 基准电流 Sine Wave Ref. Custom RoHS:否 制造商:STMicroelectronics 产品:Voltage References 拓扑结构:Shunt References 参考类型:Programmable 输出电压:1.24 V to 18 V 初始准确度:0.25 % 平均温度系数（典型值）:100 PPM / C 串联 VREF - 输入电压（最大值）: 串联 VREF - 输入电压（最小值）: 分流电流（最大值）:60 mA 最大工作温度:+ 125 C 封装 / 箱体:SOT-23-3L 封装:Reel
SWR-10-12 制造商:Raxxess 功能描述:Wall Mount 10RU Hinged Rack with 12" Usable Depth
SWR1062/C 制造商:BRITOOL 功能描述:RING SPANNER CRANK SLOG 1 1/16AF
SWR1125 制造商:BRITOOL 功能描述:RING SPANNER FLAT SLOG 1 1/8AF
SWR1187 制造商:BRITOOL 功能描述:RING SPANNER FLAT SLOG 1 3/16AF